The block structure of the computer can be best described with the following image in mind:

Block structure

The Executable ROS contains the executable kernel. It is not an operating system, it's more like a monitor and a bunch full of system routines.

The Feature ROS contains some special functions like the Sort Feature that are not used very frequently. This card is an options and not necessary for operation of the computer.

The Common and Language ROS contain code translation tables, I/O diagnostic routines as well as the APL and/or BASIC interpreter functions.

The R/W Storage is the non-permanent part of the memories with random access (RAM). The data from the display memory section can be accessed from the processor with normal memory accesses and by the graphics adaptor with Cycle Steal operations (also called Direct Memory Access). The data from RWS are gated to the processor by the Read/Write Bus lines and by the Data Bus Out lines on the Base I/O card. The other direction is by the Data Bus In lines to the processor and then by the Read/Write Bus to the RWS.

Addressing of RWS and ROS is done with the Storage Address bits, the processor address bus. Although the bus is only 16 bits wide, the processor can access more than 64kB of code in RWS and ROS (data is limited to 64kB) with a mechanism best described with "code bank switching". This is done in microcode where the fetch of the next instruction is either from RWS or ROS. Data fetches are always from RWS which makes it impossible to read out Executable ROS from within a program.

The Device Address bits are for addressing the I/O devices and not memory addresses like the Storage Address bits. The device address bus is described in the chapter Device addressing.