Computermuseum der Fakultät Informatik
Architecture of the intel 8008
Unlike contrary rumors, the i8008 is neither a "doubling" of the 4Bit
i4004 micorprocessor nor it is inspired by the PDP8.
The only doubled thing in contrast to the i4004 was the length of the
data paths. Otherwise the 4004 has the Harvard architecture, the 8008
is a vonNeumann computer. The 4004 has 16 data registers, the 8008
only 7. It is only a proof for incorrectness of the slogan "A picture
can tell more than 1000 words", that the Intel company used the same
block diagrams for their old data books with only a different
Pictures usually contribute very little to information.
Back to the i8008:
The processor has 7 registers visible for the programmer:
A, B, C, D, E, H and L. A is an accumulator, B to E are acratchpad-
registers to hold interim values, H and L are two registers to adress
The only possibility to reach the data in the memory is to interpret
the H and the L register as an indexregister of double length and to
adress it as an eighth virtual register M, which describes the byte
at the memory, which is adressed by HL.
A direct adressing of the memory is not possible, because for each
access at least the L-register hast to be loaded explicitly!
The stack is on the chip, it has 8 layers. Access is only possible by
the CALL and RETURN commands. It is not possible to save the
processors state somewhere, for example if an interrupts occurs,
and also it is not possible to save all registers.
To save the content of a register, at least the content of the L-
register has to be changed.
This and the circumstantial memory adressing via (HL) make the 8008
quite useless for general applications.
Intel defined two assembler instruction sets for the 8008. Of course,
the binary machine code remained the same for both.
The older instruction set is constructed in the way that the assembler
becomes as simple as possible: All register adresses are contained in
the OPC, which consists throughout of 3 characters. Three upper-case
characters can be encoded with 16Bits, which speeds up the browsing of
the OPC table. Additionally, Intel gave an octal description of the
machine code, what is justified because most of the commands contain two
register adresses encoded with three bits. Thus the (dis-)assembling of
the raw code by hand is eased a little bit.
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