Computermuseum der Fakultät Informatik

Details for the intel 8008

Vdd   1[       ]18   interrupt        Notice:
 D7   2[       ]17   ready             In contrast to the i8080
 D6   3[       ]16   phi 1             the 8008 only needs one 
 D5   4[       ]15   phi 2             operational voltage: -14V
 D4   5[       ]14   sync              To combine it with TTL-circuits,
 D3   6[       ]13   S0                you worked with two voltages:
 D2   7[       ]12   S1                
 D1   8[       ]11   S2                +5V and -9V. 
 D0   9[       ]10   Vcc               The reference pole is then Vdd.

Explanation of pinout:
D0-D7       Bi-directional adress/data bus.
interrupt   Activ high. Forces the processor to the interrupt-status.
ready       Aktiv high. If this pin is set to low, the
            processor is waiting for slow memory.
phi1, phi2  Two-phase clock, not overlapping. Thus the processor 
            creates an internal four-phase clock.
sync        a signal for marking the begin of the machine cycle.
S0-S2       machine state signals.

The states of the 8008:
Name S2 S1 S0    Funktion
T1    0  1  0    Lower adress-byte
T1I   1  1  0    like T1, but interrupt is recognized
T2    1  0  0    high adress-byte + cc2 and cc1
wait  0  0  0    wait for the slow memory
T3    0  0  1    data in- and output  (memory access)
stop  0  1  1    wait for interrupt
T4    1  1  1    internal data transfer
T5    1  0  1    internal data transfer

The T3-state is again differentiated by cc1 and cc2, which are 
output in T2:

Name cc2 cc1     Function
PCI   0   0      Instruction Cycle. The first byte (OPC) is read 
                 from the memory.
PCR   1   0      Read Cycle. Read data or further parts of the command
                 from the memory.
PCC   0   1      Command Cycle. Input-Output-command.
                 Input or Output depends on the adress.
PCW   1   1      Write Cycle. Write data to the memory.

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