The IBM 51x0 processor doesn't have a status register like most other
microprocessors that stores different flags reflecting the status of a
previous operation. So there are no conditional jumps that could test
e.g. the zero flag or the overflow flag. And there can't be any instruction
that explicitly modifies the flags.
Instead this processor implements a combination of test and skip instructions
that compare one or two registers and then decides whether to skip the
following instruction or not.
LBI R1, #2 LBI R2, #5 SLE R1, R2 ; The HALT instruction will be skipped HALT
LBI R1, #%11010110 LBI R2, #%01000110 LBI R3, #%00100001 LBI R4, #%01100011 SBS R1, R2 -> skip SBS R1, R3 -> no skip SNBS R1, R3 -> skip SNBS R1, R4 -> skip SNBC R1, R3 -> no skip SNBC R1, R4 -> skip SBC R1, R3 -> skip